Lead/Principal DFT Engineer
Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.
Define and lead the end-to-end DFT architecture for a large, multi-core AI accelerator SoC, taking ownership from early strategy through silicon bring-up and production. This role combines architectural leadership with hands-on execution, ensuring scalable, power-aware, and high-coverage test solutions while driving alignment across design, physical implementation, and test engineering teams.
Key Responsibilities
Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan)
Set DFT strategy, methodology, flow and signoff criteria
Drive integration of DFT tools and flows into the overall EDA environment
Define hierarchical DFT approach for multi-core designs and large memory systems
Define scan architecture, compression strategy, and ATPG approach
Define memory test and repair strategy for large embedded RAM
Establish power-aware and at-speed test strategies
Work closely with RTL and physical design to ensure clean DFT integration and timing closure
Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
Mentor and guide DFT engineers
Required Experience
Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years)
Proven ownership of DFT architecture on at least one large tapeout
Deep expertise in scan, compression, ATPG, and MBIST
Experience with industry tools (Synopsys or Tessent)
Strong understanding of clocking, resets, power domains, and physical constraints
Experience with silicon bring-up, debug, and yield ramp
Profile
Comfortable owning ambiguous, high-impact problems
Balances architectural thinking with hands-on execution
Sets direction while staying close to implementation details
About us
Founded in 2022, team of 80+ which is expanding rapidly
Modern, open offices in London and Bristol
Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance
Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.
Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years)
Proven ownership of DFT architecture on at least one large tapeout
Deep expertise in scan, compression, ATPG, and MBIST
Experience with industry tools (Synopsys or Tessent)
Strong understanding of clocking, resets, power domains, and physical constraints
Experience with silicon bring-up, debug, and yield ramp
Profile
Comfortable owning ambiguous, high-impact problems
Balances architectural thinking with hands-on execution
Sets direction while staying close to implementation details
Apply with uptayn.
Sign in free to open the apply link, get this role scored against your CV, and track your application.