Senior Simulation Engineer

Bristol

Bristol or London, 3 days in the office, 2 days WFH

At Fractile, we’re building what we believe will be the world’s fastest AI inference chip from the ground up. We’re balanced across hardware and software engineering, and HW/SW co-design is real here. We move fast, and we help each other move fast. We care about each other, the software we ship, and the people who rely on it.

To validate behaviour, our functional simulator allows us to iterate at scale with real software before the hardware exists. It runs across multiple machines, supports large experiments, and helps verify the correctness of our low level firmware, runtime stack and compiler lowering.

You’ll be there for the first end-to-end runs against realistic device behaviour, the debugging sessions that unblock whole teams, and the moments where simulator fidelity turns into better software, better silicon decisions, and faster bring-up.

What you’ll do

Build a functional simulator of Fractile’s AI accelerator hardware including a custom ISA

Implement the device models and behaviours that matter for software correctness: MMIO, interrupts, DMA, memory behaviour, concurrency, and error paths

Work closely with runtime, kernel, firmware and HW engineers to shape simulator interfaces

Make it usable at scale: tracing, determinism/reproducibility, CI integration, and containerised workflows

Collaborate daily with hardware, software, and ML engineers to validate assumptions and close gaps early

What we’re looking for

Strong C and comfort working in large low-level codebases

Good intuition and knowledge of low-level hardware behaviour: registers/MMIO, interrupts, memory ordering, concurrency, and failure modes

You enjoy hard system-level problems, and you take them end-to-end until the results are measurable

Computer Science, Electronic Engineering, Maths, Physics, or related degree and 3+ years of industry experience

Nice to have

You’ve built or extended hardware simulators or emulators.

SystemC experience

QEMU device model experience is ideal, even better in the TCG

Docker and orchestration tooling (Kubernetes)

Familiarity with RISC-V and x86 architectures

Python experience useful

If you want to build the simulator that makes rack-scale software real before rack-scale hardware exists, come build it together.