Design Verification Engineer

<h6>Project Description:<br></h6><p>As Design Verification Engineer, you will join leading-edge team responsible for the verification of advanced interconnect systems in state-of-the-art microprocessors. This role focuses on ensuring the functionality, performance, and reliability of high-bandwidth data communication architectures.<br><br>We are looking for someone who has a passion for modern, complex processor architecture, digital design, and verification in general. Who are a team player and has good communication skills, strong analytical and problem-solving skills and willing to learn and ready to accept challenges.</p><div><h6>Skills required:<br></h6><div><p>-Minimum of 5 years experience in Digital Design Verification<br>-Strong skills with System Verilog and UVM. Good skills with Verilog<br>-Exposure to both maintaining an existing Verification Environment as well as creating one from scratch<br>-Experience with functional verification tools by VCS, Cadence, Mentor Graphics<br>-Experience working in a Unix/Linux environment<br>-Good scripting skills (Perl, Shell, Ruby)</p></div></div><div><h6>Nice To Have:<br></h6><div><p>-Proven experience of working with complex designs (not just I2C and other similar designs) would be an asset<br>-Good computer architecture, cache coherency knowledge would be an asset<br>-Exposure to simulation profile, efficiency improvement, acceleration would be an asset<br>-Exposure to leadership or mentorship would be an asset</p></div></div><div><h6>Responsibilities:<br></h6><div><p>-Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs<br>-Develop, document and execute on verification test plans at unit level of design hierarchy<br>-Develop high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog<br>-Develop, simulate and debug directed/random stimulus to ensure design functionality according to specifications</p></div></div>